Progress Report of Region3

.
 
1) VDC drawings

First version of engineering drawings of  all VDC frames and assembly has been completed.
Some details have to discussed with JLab engineers and JLab machine shop for the next 2 weeks (like O-Ring dimension or some machining aspects) before
the the drawings are send out for bids


Pic below: The VDC is embedded inside an aluminum Faraday cage for optimal background noise shielding.
                 The frontend electronics (MAD chips: Preamp+Discrimitator) is located inside the shielding box.



Pic below: Layout of the frontend electronics for reading out one wire plane.
                 The 8 MAD boards will be located on a  PCB  handling the digital signal multiplexing (Delayline readout) .
                 In addition each digital output is accessable individually (for direct readout w/o multiplexing)


Pic below: Location of U and V plane Frontend electronics


Pic below: Details of the VDC cross section




Most of the time is spend on generating detailed engineering drawings in 2D from the 3D SolidWorks  models, so JLab engineers can review then.
(Drawings: Inner_HVPlane.pdf , Outer HVPlane.pdf , WirePlane.pdf , BasePlate.pdf)



2) GEANT4 simulation progress

-To be done:  running the frozen (?!) collimator design through Geant4 and check the tracking efficiency.
                     Tracking efficiency can be tweaked a bit by changing the wire angle slightly.


- Seens like Jeff Martin is setting up a Cerenkov simulation for testing a  luminosity scanner using  the QweakSim Geant4 code (elog).

3) Progress on the Wire Scanner

  Joe Katich negotiated with several companies about quotes for a pre-build translation stage. First quotes were in the range of 5 - 17k and scale with the travel range.
  This week we ordered an assembled translation stage from LinTech (5k$). Instead of choosing a very precise and expensive preloaded ball screw (no backlash), the
  overall precision is given by attaching a linear position encoder (4um overall precision). Therefore the scan should be done in one direction only to avoid backlash
  (or go back to a well defined start position). Even one step of the stepper motor (1.8deg) with give a lead of 25um, the field of view optics is sufficient enough
  to resolve at least 10um and better on the screen. The scanner has a travel range of 48" and is shorter than the inner length of the VDC. For scanning all VDC wires we
   have to place the scanner at various locations defined by precision dowel pins and markers.
    
4) Progress on Garfield Simulation
Carissa cleaned up the code and wrote a summary about her Garfield work and the programs she has developed. Last week she succeded with the help of the Garfield author
Rob Veenhof to simulate the induced wire signal. Currently she is optimizing the code ( avalance related part for the signal amplification) in order to figure out
the current, charge and gain sensitivity.

 

5) Misc

Our new W&M graduate student  Pjerin Luli just arrived this week. One of the first summer projects is about building and programing a computer interface (Parallel Port <->I2C bus,
~serial bus) for talking to the local MAD chip controller PCF8574  (for dis/enabling individual channels, etc).

6) Frontend Electronics

Chris Cueva and I discussed the delevopment of a frontend board for the wire signal readout using the MAD chip and how to implement a multiplexed readout
(Chris has some ideas besides the classic delay line readout).
At present I'm putting together all the italian/english MAD chip information and dimensional restrictions from the VDC design needed for the board design.
CAEN send me a quote for the MAD chip: 33$/chip = 8.25$ per channel. Next week we will order 600 chips (~20k$) from CAEN, lead time is up to 12 weeks ...


That's all folks !